发明名称 Prüfvorrichtung, Prüfverfahren, Programm und Aufzeichnungsmedium
摘要 There is provided a test apparatus for testing a memory under test that is addressable by the number of pulses of an address signal supplied thereto. The test apparatus includes a pattern generating section that generates writing data to be written into the memory under test, a first address generating section having an address information storing section that stores thereon address information indicating an address of the memory under test to which the writing data is to be written, and a waveform shaping section that generates an address signal by outputting one or more pulses at a predetermined time interval during a time period determined in accordance with the address information stored on the address information storing section.
申请公布号 DE112006002481(T5) 申请公布日期 2008.07.10
申请号 DE20061102481T 申请日期 2006.08.24
申请人 ADVANTEST CORP. 发明人 FUJIBE, TASUKU;WATANABE, NAOYOSHI;HASHIMOTO, JUN
分类号 G11C29/10;G01R31/28;G11C29/56 主分类号 G11C29/10
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