| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can prevent interference between adjacent bit lines on a memory cell plate by changing a wiring pattern of column selection signal lines in a layout of the conventional memory cell plate and a peripheral circuit. SOLUTION: Write performance can be improved by defining the wiring layout of the column selection signal lines 20 and 21 in such a way that a pair of bit lines BL5 and /BL5 (not driven simultaneously with BL0, /BL0, BL2, and /BL2) corresponding to the other column selection signal 21 are arranged between pairs of bit lines BL0, /BL0, BL2, and /BL2 which are driven simultaneously and selected in the memory cell plate 11 by the column selection signal line 20, thus preventing capacity coupling due to inter-line capacitance of the adjacent bit lines. COPYRIGHT: (C)2008,JPO&INPIT
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