发明名称 SAMPLE AND HOLD CIRCUITS AND METHODS WITH OFFSET ERROR CORRECTION AND SYSTEMS USING THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a sample and hold circuit suitable for mixed signal processing. SOLUTION: A sample and hold circuit includes a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor, and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008160843(A) 申请公布日期 2008.07.10
申请号 JP20070328033 申请日期 2007.12.19
申请人 CIRRUS LOGIC INC 发明人 PRASAD AMMISETTI V;THOMPSON KARL;MELANSON JOHN LAURENCE;SOMAYAJULA SHYAM
分类号 H03M1/12;G11B20/10;G11C27/02;H03K17/00 主分类号 H03M1/12
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