发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To properly suppress the increase of the circuit size of a PLL circuit for generating a clock synchronized with one of the first reference signal where a land pre-pit signal is overlapped to a wobble signal and the second reference signal consisting of a wobble signal. SOLUTION: When an optical disk 1 is a DVD-R/RW, in the first loop A, a frequency-divided clock of an oscillating clock of a voltage controlled oscillator 110 is frequency-synchronized with the wobble signal. Also in the second loop B, the frequency-divided clock of the oscillating clock of the voltage controlled oscillator 110 is phase-synchronized with a LPP signal. On the contrary, when the optical disk 1 is a DVD+R/RW, in the first loop A, the frequency-divided clock of the oscillating clock of the voltage controlled oscillator 110 is frequency-synchronized with the wobble signal. Also, in the second loop B, fixed voltage is applied to a control voltage input terminal (b) of the voltage controlled oscillator 110. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008159265(A) 申请公布日期 2008.07.10
申请号 JP20080034900 申请日期 2008.02.15
申请人 SANYO ELECTRIC CO LTD 发明人 KIYOSE MASASHI;SHIRAISHI TAKUYA
分类号 G11B20/14;G11B7/004;G11B20/10 主分类号 G11B20/14
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