发明名称 |
Method of Forming Trench Gate FETs with Reduced Gate to Drain Charge |
摘要 |
A method for forming a FET includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A well region of a second conductivity type is formed in the semiconductor region. Source regions of the first conductivity type are formed in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches. A gate dielectric layer having a non-uniform thickness is formed along the opposing sidewalls of the trenches such that a variation in thickness of the gate dielectric layer along at least a lower portion of the channel regions is: (i) substantially linear, and (ii) inversely dependent on a variation in doping concentration in the lower portion of the channel regions. A gate electrode is formed in each trench.
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申请公布号 |
US2008166846(A1) |
申请公布日期 |
2008.07.10 |
申请号 |
US20080052135 |
申请日期 |
2008.03.20 |
申请人 |
FAIRCHILD SEMICONDUCTOR CORPORATION |
发明人 |
MARCHANT BRUCE D.;CHALLA ASHOK |
分类号 |
H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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