发明名称 |
ACCESSING MEMORY USING MULTI-TILING |
摘要 |
<p>An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.</p> |
申请公布号 |
WO2008083364(A1) |
申请公布日期 |
2008.07.10 |
申请号 |
WO2007US89170 |
申请日期 |
2007.12.28 |
申请人 |
INTEL CORPORATION;AKIYAMA, JAMES;CLIFFORD, WILLIAM |
发明人 |
AKIYAMA, JAMES;CLIFFORD, WILLIAM |
分类号 |
G06F12/02;G06F12/06 |
主分类号 |
G06F12/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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