METHOD FOR DESIGNING POWER SAVING CIRCUIT USING CLOCK GATING AND THEREFOR POWER SAVING CIRCUIT

摘要

A power saving circuit using clock gating and a design method thereof are provided to implement a low-power circuit using less power of a battery in a portable electronic device by using an ICGC(Integrated Clock Gating Cell) for outputting a clock signal to a clock pin of a plurality of FIFOs(First Input First Output). A register bank(400) comprises a plurality of FIFOs. A plurality of XOR gates(410) receive data from an I/O(Input/Output) unit of the FIFOs through different pins. An OR gate(420) includes a plurality of input pins for receiving output of the XOR gates. An ICGC circuit(460) outputs a clock signal to a clock pin of the FIFOs by receiving the output and the clock signal of a first AND gate(430) and using the output of the first AND gate as an enable signal. The ICGC circuit includes a latch(440) receiving the output of the first AND gate as input and receiving the clock signal through an enable pin via an inverter, and a second AND gate(450) outputting the output and the clock signal of the latch to the clock pin of the FIFOs.