Semiconductor memory device

摘要

In addition to a booster power supply circuit boosting a power (11) supply voltage to supply a boost voltage VPP to a memory core (12), cell capacitors composing a stabilization capacitor, and a bias generation circuit (13) supplying a midpoint potential to a connection point of the cell capacitors, further, a clamp circuit (15) reducing the boost voltage to a set value is provided, in which when the booster power supply circuit (11) stops a boosting operation, the clamp circuit (15) clamps the boost voltage to the set value, so that the midpoint potential can be prevented from largely deviating to a boosting voltage side and a ground potential side in a transition to a normal operation thereafter.