| 摘要 |
<P>PROBLEM TO BE SOLVED: To reliably evaluate access for defective expected value patterns at a predetermined timing including the correction delay by ECC operations. <P>SOLUTION: The nonvolatile memory has read means 25, 30, and 32 to asynchronously read the data stored in a memory cell array 20, a defective position selector circuit 40 to find out defective positions and to output the defective position selection signals, a defect generator circuit 50 which degrades and output a part of the data in the output data of the above read means in response to the above defective position selection signals and when the above test mode signal is active, while outputting the output data of the above read means as it is when the above test mode signal is not active, a data latch circuit 58 to latch the output data of the above defect generator circuit 50, and an ECC59 to detect and correct the errors in the output data of the above data latch circuit 58. <P>COPYRIGHT: (C)2008,JPO&INPIT |
