| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve the problem that a locked period of a DLL circuit may become long when switching a semiconductor device to be activated in a clock generating circuit using the DLL circuit. <P>SOLUTION: A delay adjustment circuit of the DLL circuit is constituted of a fixed-length delay circuit and N pieces of variable-length delay circuits. Internal clocks are supplied to N pieces of semiconductor devices. A delay difference of the N pieces of variable-length delay circuits is made equal with a delay difference for the N pieces of semiconductor devices. For selected semiconductor devices, delay clocks from the N pieces of variable-length delay circuits are selected so as to eliminate the delay difference. <P>COPYRIGHT: (C)2008,JPO&INPIT |
