| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase synchronizing circuit achieving high-speed calibration. <P>SOLUTION: A VCO 16 oscillates at a frequency fosc corresponding to an input control voltage Vcnt and includes regulation capacitors 50a and 50b for varying an oscillation frequency fosc for a certain control voltage Vcnt. A frequency divider 18 frequency-divides the output signal OUT of the VCO 16 so as to be synchronized with the frequency of a predetermined reference clock REF. A phase comparing unit 2 compares the phase of the output signal OUT 2 of the frequency divider 18 with the phase of the reference clock REF and outputs a voltage corresponding to the phase difference as a control voltage Vcnt to the VCO 16. A capacity regulating unit 30 regulates the capacity value of a regulation capacitor 50 so that the control voltage Vcnt is within a predetermined voltage range in a frequency-locked state during a predetermined calibration period. A loop control unit 40 varies loop characteristics of the phase synchronizing circuit 100 between the calibration period and a normal operation period. <P>COPYRIGHT: (C)2008,JPO&INPIT |
