发明名称 |
CONTROL VOLTAGE DETERMINING METHOD OF INTEGRATED CIRCUIT, GATE VOLTAGE DETERMINING METHOD OF TEG CIRCUIT, TEG CIRCUIT TESTING METHOD AND TESTING DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To provide an integrated circuit and a TEG (Test Element Group) circuit hard to be affected by the impact on circuit operation caused by property variation or fluctuation of a transistor such as a threshold voltage. SOLUTION: A current mode operation circuit comprises a pair of resistor devices MP1 and MP2, a pair of N type differential transistors MN1 and MN2, and a current source transistor ML for supplying operation current to the pair of N type differential transistors. The control voltage VL of the current flowing to the current source transistor is determined so that the voltage gain of the integrated circuit will become at least one or more, in relation to property variations such as the threshold voltage of the N type differential transistors. COPYRIGHT: (C)2009,JPO&INPIT
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申请公布号 |
JP2008294547(A) |
申请公布日期 |
2008.12.04 |
申请号 |
JP20070135540 |
申请日期 |
2007.05.22 |
申请人 |
AGILENT TECHNOL INC |
发明人 |
ENDO TETSUO;SASAKI KATSUTO;UTADA KAZUHISA |
分类号 |
H03K19/0944;G01R31/26;G01R31/316;H03F3/45 |
主分类号 |
H03K19/0944 |
代理机构 |
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代理人 |
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地址 |
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