| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a microprocessor for performing cache hit about both an unexecuted instruction and an executed instruction. <P>SOLUTION: In a microprocessor, a prefetch buffer 6 stores an instruction prefetched from an SDRAM 2. A buffer control part 16 decides whether a branch destination instruction is present in the prefetch buffer 6 on the basis of a top pointer in a first register 10 showing a write address and a read pointer in a second register 12 showing a read address and a bottom pointer in a third register 14 showing the storage address of the oldest effective instruction, and when the branch destination instruction is present, changes the value of the read pointer so that the address of the branch destination instruction can be designated, and when the branch destination instruction is not present, resets the values of the top pointer, the read pointer and the bottom pointer to initial values, and makes a prefetch buffer 6 prefetch the branch destination instruction. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
