| 摘要 |
PROBLEM TO BE SOLVED: To reduce the occurrence of a timing defective chip, to a rate lower than a prescribed market defect rate required. SOLUTION: The statistical timing analysis device 30 is provided with a circuit net list part 1, a timing asserting part 2, a delay mode part 3, a variable factor statistical information part 4, an SSTA execution part 5, a variation reference specification generating part 6, and a comparison and determination part 7. The SSTA executing part 5 inputs the information from the circuit net list part 1, the timing asserting part 2, the delay model part 3, and the variable factor statistical information part 4, executes statistical timing analyses, and calculates the defect probability of the semiconductor integrated circuit chip, from a variation reference specification table, generated in advance. The variation reference specification generating part 6 inputs the quality product probability calculated by the SSTA execution part 5, and generates the variation reference specification table. The comparison and determination part 7 compares the defect probability of the semiconductor integrated circuit chip with the prescribed defect rate, and determines as an operation timing quality product when the defect probability is lower than the prescribed defect rate, and determines as an operation timing defective product, when the defect probability is higher. COPYRIGHT: (C)2009,JPO&INPIT
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