| 摘要 |
A semiconductor process and apparatus provide a planarized hybrid substrate (16) by selectively depositing an epitaxial silicon layer (70) to fill a trench (96), and then blanket depositing silicon to cover the entire wafer with near uniform thickness of crystalline silicon (102) over the epi silicon layer (70) and polycrystalline silicon (101, 103) over the nitride mask layer (95). The polysilicon material (101, 103) added by the two-step process increases the polish rate of subsequent CMP polishing to provide a more uniform polish surface (100) over the entire wafer surface, regardless of variations in structure widths and device densities. By forming first gate electrodes (151) over a first SOI layer (90) using deposited (100) silicon and forming second gate electrodes (161) over an epitaxially grown (110) silicon layer (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility. ® KIPO & WIPO 2009 |
