发明名称 Integrated circuit packages with reduced stress on die and associated methods
摘要 Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed of a relatively higher yield strength material, such as copper, having a relatively higher melting point than the component contacts and having a relatively high current-carrying capacity. The component contacts may be hemispherical in shape. The lands may be substantially cylinders, truncated cones or pyramids, inverted truncated cones or pyramids, or other columnar shapes. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
申请公布号 US7465651(B2) 申请公布日期 2008.12.16
申请号 US20050173585 申请日期 2005.06.30
申请人 INTEL CORPORATION 发明人 AGRAHARAM SAIRAM;HANNA CARLTON;ATLURI VASUDEVA;HE DONGMING
分类号 H01L21/44;H01L21/60;H01L23/485;H01L23/498;H05K1/11;H05K3/34;H05K3/40 主分类号 H01L21/44
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