| 摘要 |
<p>An internal clock driver circuit is provided to solve data distortion problem by DLL(Dynamic Link Library) clock signal by removing an overlap of rising DLL clock and falling DLL clock. An internal clock driver circuit comprises a delay unit(100), a rising DLL clock generator(200), and a falling DLL clock generator(300). The delay unit outputs a delay rising clock and a delay falling clock by delaying a rising clock and falling clock. The rising DLL clock generator outputs a rising DLL clock by assembling the rising clock, the falling clock, and the delay rising clock. The falling DLL clock generator outputs a falling DLL clock by assembling the rising clock, the falling clock, and the delay falling clock.</p> |
