| 摘要 |
The invention relates to an equalised time interleaved analogue digital conversion device. The analogue digital conversion device comprises a number N of analogue digital converters distributed in N channels. Each analogue digital converter has a sampling frequency N times lower than the required sampling frequency. The digital signal is built up from samples output from each channel. The device comprises a reference channel comprising an analogue digital converter generating samples of the analogue signal. Each filter comprises an equaliser filter. The filter received a digital signal output by the analogue digital converter of the channel on which it is placed. The filter also receives an error signal and outputs a filtered digital signal s(n) corrected for errors deduced from the error signal. The error signal corresponds to the difference at a given time between firstly the digital signal corrected by the filter and secondly by the digital signal output by the analogue digital converter of the reference channel. In particular, the invention is applicable to analogue digital converters operating at a high clock frequency, typically of the order of one gigahertz.
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