发明名称 Methods and apparatus for compiler managed first cache bypassing
摘要 Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.
申请公布号 US7467377(B2) 申请公布日期 2008.12.16
申请号 US20020278682 申请日期 2002.10.22
申请人 INTEL CORPORATION 发明人 WU YOUFENG;CHEN LI-LING
分类号 G06F9/45;G06F9/00;G06F12/00;G06F12/08 主分类号 G06F9/45
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