| 摘要 |
According to one embodiment, a pipeline high-level synthesis system receives a high-level description and performs pipeline high-level synthesis for its loop description part to generate a pipelined circuit having a structure in which a plurality of combinational logic parts serially arranged are separated by pipeline registers. If a memory access conflict is caused by a plurality of combinational logic parts including memory accesses in the circuit generated by the first circuit section, the system allows the logic parts in which a memory access conflict occurs to access a memory through a shift register having a size corresponding to the combinational logic parts.
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