发明名称 Common pass gate layout of a D flip flop
摘要 A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.
申请公布号 US7465970(B2) 申请公布日期 2008.12.16
申请号 US20060382700 申请日期 2006.05.10
申请人 FARADAY TECHNOLOGY CORP. 发明人 WU JENG-HUANG;FENG CHIUNG-YU;HUANG CHIEN-CHIH;TSAI YU-WEN
分类号 H01L27/02;H01L27/10 主分类号 H01L27/02
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