发明名称 Shared memory bus architecture for system with processor and memory units
摘要 A system is provided for testing a first integrated circuit associated with at least a second integrated circuit in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuits, and wherein the first integrated circuit is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit when the first integrated circuit is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit or an associated external terminal when the first integrated circuit is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit to transition between normal operation and the test mode.
申请公布号 US7466160(B2) 申请公布日期 2008.12.16
申请号 US20060472016 申请日期 2006.06.20
申请人 发明人
分类号 G01R31/28;G11C7/00;G11C29/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址