发明名称 Synchronizing PCM and pseudorandom clocks
摘要 In a system having a received PN clock signal, a method is disclosed for providing a synchronized system clock signal having reduced jitter wherein the synchronized system clock signal is synchronized with the received PN clock signal. The method includes providing a stable high frequency reference signal and dividing the high frequency reference signal to provide a system clock signal having a plurality of system clock phases. The method also includes adjustably selecting a system clock phase of the plurality of system clock phases in accordance with the received PN signal in order to provide the synchronized system clock signal. The received PN clock signal is recovered by providing PN phase adjustments of the received PN clock signal. A tracking control signal is provided in accordance with the PN phase adjustments and the system clock phase is adjustably selected in accordance with the tracking control signal. The high frequency reference signal can be multiplied prior to the dividing.
申请公布号 US7466745(B2) 申请公布日期 2008.12.16
申请号 US20030706369 申请日期 2003.11.12
申请人 INERTDIGITAL CORPORATION 发明人 KAEWELL JOHN
分类号 H04B1/00;H04L7/033;H03L7/06;H03L7/18;H03L7/23;H04B7/26;H04J3/06 主分类号 H04B1/00
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