发明名称 |
SEMICONDUCTOR FABRICATION PROCESS USING ETCH STOP LAYER TO OPTIMIZE FORMATION OF SOURCE/DRAIN STRESSOR |
摘要 |
<p>A semiconductor fabrication process includes forming an etch stop layer (ESL) (109) overlying a buried oxide (BOX) layer (102) and an active semiconductor layer (105) overlying the ESL. A gate electrode (112) is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors (130) are formed on the ESL where the source/drain stressors strain the transistor channel (115). Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75‹ C may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors. ® KIPO & WIPO 2009</p> |
申请公布号 |
KR20080108498(A) |
申请公布日期 |
2008.12.15 |
申请号 |
KR20087023819 |
申请日期 |
2008.09.29 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
ZHANG DA;WHITE TED;NGUYEN BICH YEN |
分类号 |
H01L29/78;H01L21/336 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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