发明名称 |
POWER DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT WITH THE SAME |
摘要 |
A power down mode control apparatus and a DLL circuit with the same is provided to reduce noise in the power down mode, so realizing the stable power-down mode. In a power down mode control apparatus(90), an internal power control(902) receive a locking signal and an internal power down signal for toggling it for a certain time. A noise monitoring unit(904) checks noise generation from a phase sensing signal and generates a plurality of power down selection signals in response to the locking signal and the internal power down signal. A power down entry control unit(906) controls the respective circuit to enter the power down mode in response to a reference clock, a plurality of power down selection signals, power down mode signal and internal power down signal.
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申请公布号 |
KR100873624(B1) |
申请公布日期 |
2008.12.12 |
申请号 |
KR20070114147 |
申请日期 |
2007.11.09 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
LEE, HYUN WOO;YUN, WON JOO;SHIN, DONG SUK |
分类号 |
G11C5/14;G11C8/00;G11C11/407 |
主分类号 |
G11C5/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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