| 摘要 |
<p>A method of generating a voltage as well as an integrated circuit device having a memory cell array which Includes a plurality of memory cells, wherein each memory cell array including a plurality of memory cells, arranged in a matrix of rows and columns, and a plurality of bit lines, wherein each bit line includes a plurality of memory cells The integrated circuit further Includes voltage generation circuitry, coupled to a plurality of the bit lines, to apply a first voltage to a first group of associated bit lines, and apply a second voltage to a second group of associated bit lines, and generate a third voltage by connecting the first and second groups of associated bit lines, and output the third voltage Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry</p> |
