发明名称 |
DELAY LOCKED LOOP CIRCUIT |
摘要 |
A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
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申请公布号 |
US2008303567(A1) |
申请公布日期 |
2008.12.11 |
申请号 |
US20080033707 |
申请日期 |
2008.02.19 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
SAKIYAMA SHIRO;TOKUNAGA YUSUKE;DOSHO SHIRO;IWATA TORU;HIRATA TAKASHI;YOSHII HIDEKI;DOI YASUYUKI;HATTORI MAKOTO |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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