| 摘要 |
PROBLEM TO BE SOLVED: To make it possible to perform delay and failure test by generating original launch clock and capture clock of original pulse width, according to time constraints. SOLUTION: This semiconductor integrated circuit device comprises a plurality of flip-flops, an oscillator that outputs oscillating output, a memory portion that stores control data for the delay and failure test, a launch clock that maintains relation with the shortest period in at least one place, a first generation portion that generates first control signals that form combinations of clocks consisting of a plurality of capture clocks, a second generation portion that generates second control signals that form combination of clocks that maintain relation with the shortest period in a second place, an output portion that generates combinations of clocks, based on the first and second control signals and the oscillating output, and a control means that gives first and second control signals selectively. The foregoing are the main features of this invention. COPYRIGHT: (C)2009,JPO&INPIT
|
