<p>A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.</p>
申请公布号
WO2008150889(A1)
申请公布日期
2008.12.11
申请号
WO2008US65120
申请日期
2008.05.29
申请人
MAGMA DESIGN AUTOMATION, INC.;BANERJEE, JOY;JIANG, YUNJIAN;SRINIVASAN, ARVIND;LI, YINGHUA;DAS, PARTHA;CHAUDHURI, SAMIT