发明名称 |
COMPUTATIONALLY EFFICIENT MATHEMATICAL ENGINE |
摘要 |
A method and apparatus perform many different types of algorithms that utilizes a calculation unit capable of utilizing the same multipliers for different algorithms. The calculation unit preferably includes a processor that has a plural number of arithmetic logic unit circuits that are configured to process data in parallel to provide processed data outputs and an adder tree configured to add the processed data outputs from the arithmetic logic circuits. A shift register that has more parallel data outputs then the processor's inputs is controlled to selectively output data from the parallel outputs to the data inputs of the processor. A communication device preferably includes the calculation unit to facilitate processing of wireless communication signals.
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申请公布号 |
US2008307205(A1) |
申请公布日期 |
2008.12.11 |
申请号 |
US20080194975 |
申请日期 |
2008.08.20 |
申请人 |
INTERDIGITAL TECHNOLOGY CORPORATION |
发明人 |
BUCHERT RYAN SAMUEL;TIMMERMAN CHAYIL S.;SUPPLEE STEPHAN SHANE |
分类号 |
G06F7/38;G06F5/01;G06F7/00;G06F7/52;G06F17/16;G06K |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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