| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide circuit and a method for programmable integer clock division with 50% duty cycle. <P>SOLUTION: The present invention relates to circuits and a method for dividing a frequency of an input signal by an integer divider value. The circuit generally comprises (a) a first frequency divider, including a first plurality of serially connected delay elements receiving the input signal and a first configurable feedback network, (b) a second frequency divider, including a second plurality of serially connected delay elements receiving an inverse of the input signal and a second configurable feedback network, (c) configurable logic configured to select and/or combine outputs of the first and second frequency dividers and to produce a frequency divided output signal, and (d) a programmable circuit configured to selectably configure the first and second configurable feedback networks and the configurable logic. <P>COPYRIGHT: (C)2009,JPO&INPIT |
