PROCESSOR ARRAY SYSTEM HAVING FUNCTION FOR DATA REALLOCATION BETWEEN HIGH-SPEED PE

摘要

A processor array system which is able to perform load balancing among PEs at high speed is provided. When an instruction code 113, "MVLR", is sent from a control processor 110, in a PE having a mask register MR being in operation setting, in case wherein the direction register F is ON, if a counter and transfer result storing buffer T is greater than or equal to M, a value of T - M is stored in T, and if T is less than M, content of a first transport register L of a PE whose PE number counted from the left inside a PE block is T, is selected by a first selector LS to be stored to in to a transfer result buffer T and the mask register is set to non-operation. On the other hand, in case wherein the direction register F is OFF, if T is less than or equal to -M, a value of T + M is stored in T, and if T is greater than -M, content of R of a PE whose PE number is -T, counted from the right inside the PE block, is selected by a second selector RS to be stored in T, and MR is set to non-operation. Next, entire PEs use B0 and B1 to transfer content of L and R to M-adjacent left and right PEs, and data transferred from M-adjacent right and M-adjacent left PEs are stored in L and R respectively. Since these operations are generally simple, they can be completed in one step. On the other hand, the control processor 110 continues to send the same instruction code "MVLR" each step to PEs, until the MRs of entire PEs become non-operation setting.