发明名称 Logic circuit and method for performing AES MixColumn transform
摘要 A logic circuit having structure for performing the AES Rijndael MixColumns transform exploits the relationship between each successive row of the transform matrix and its preceding row. Multiplication of an (m.times.n) matrix by a (1.times.n) or by a (m.times.1) matrix is performed, where m is a number of rows and n is a number of columns, and where each successive row, m, of n elements is a predetermined row permutation of a preceding row, includes: n multiplication circuits; n logic circuits; n registers for receiving logical output from the logic circuits; feedback logic for routing contents of each register to a selected one of inputs of the logic circuits in accordance with a feedback plan that corresponds to the relationship between successive matrix rows; and a control unit for successively providing as input to each of the n multiplication circuits each element in the (1.times.n) or (m.times.1) matrix.
申请公布号 US7464130(B2) 申请公布日期 2008.12.09
申请号 US20040516846 申请日期 2004.12.03
申请人 NXP B.V. 发明人 HUBERT GERARDUS T. M.
分类号 G06F7/52;G09C1/00;G06F7/72;H04L9/06 主分类号 G06F7/52
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