| 摘要 |
The application discloses cascaded, iterative CRC calculation circuits whereby the CRC calculation is subdivided into blocks with selectable bus widths. The advantage is to provide parallel CRC calculation for a bus width of any arbitraty number of bytes, i.e. for vaariable bus width. One embodiment is a system for generating CRC codewords associated with data ranging up to w-bytes width including a first plurality of serially coupled code-generation blocks, respective blocks configured for receiving data inputs with byte widths from 2N + M to 2N-L+ M, where N=log2(w), and M is an offset value, and L is a whole number based on a maximum propagation delay criteria; a second plurality of parallel coupled code-generation blocks, respective blocks configured for receiving data with byte widths from 2N-L - 1 + M to 2.degree.; and, a device for selecting particular code-generation blocks in the first and second pluralities to be included in a CRC calculation. <IMG>
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