| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory that constitute a layered memory cell array and can contain memory cells arranged at high density and can prevent the reduction of working speed that may be caused by an increased bit line resistance. <P>SOLUTION: The semiconductor memory comprises a word line WL, a global bit line GBL intersecting the word line WL, a local bit line LBL divided into N lines along with the global bit line GBL, an N pieces of memory cell arrays containing a plurality of memory cells MCs having a vertical NMOS transistor N0 which is formed on the intersection of the word line WL and a local bit line LBL and connected to the local bit line LBL arranged below, a local sense amplifier 12 which amplifies a signal read from the memory cell MC to the local bit line LBL, and a global sense amplifier 11 which connects a signal transmitted from the local sense amplifiers 12 via the global bit line GBL to input/output lines. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
