| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which avoids cracks due to pressures applied on a pad due to bonding or the like. <P>SOLUTION: Metal wiring patterns WP constituting semiconductor device circuits achieves a multilayer interconnection structure at an inner circuit side via interlayer dielectric layers IL and vias VIA. A dummy pattern forbidden region PROH is provided immediately beneath a region forming the metal pad PAD on an extension of such a multilayer interconnection. Specifically, the metal pad PAD is provided on the dummy pattern forbidden region PROH, wherein the metal pad is connected to the semiconductor device circuits through the interlayer dielectric layers IL and has an electrically connected region to an outside. Ranges covered by predetermined distances d1 around a lower part of the PAD are constituted to be fully buried by the interlayer dielectric layers IL. An impact caused when bonding to the metal pad PAD is exerted on the interlayer dielectric layers IL which is buried on the dummy pattern forbidden region PROH. <P>COPYRIGHT: (C)2009,JPO&INPIT |
