| 摘要 |
A data transfer apparatus includes a processor, a main memory, and a DMAC connected to the main memory via a plurality of buses. The DMAC transfers data to the main memory by bypassing the processor, writes flag data "1" indicating completion of the data transfer processing in a completion status storage area of the main memory, and finally outputs an interrupt signal to the processor. In response to the interrupt signal, an interrupt handler refers to the completion status storage area, and when the flag data is written, reads the data in the main memory and erases the flag data in the completion status storage area.
|
