PROCESSOR SYSTEM, BUS CONTROLLING METHOD, AND SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among a plurality of master units accessing the shared memory. SOLUTION: The multiprocessor system includes: a plurality of master units PU 0 and PU 1 each of which issues an access request for accessing the shared memory; and a bus IF unit 4-10 which accesses a bus by a split transaction scheme and separately executes a request phase for accepting the access request and a transfer phase for executing data transfer in response to the accepted access request. In the case where one of the master units consecutively issues a plurality of access requests without an interval of a predetermined time period, the bus IF unit 4-10 restricts the number of consecutive transfer phase executions corresponding to the plurality of access requests to be not more than N. COPYRIGHT: (C)2009,JPO&INPIT