发明名称 ENCRYPTION/DECRYPTION DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a encryption/decryption device in which circuit scale is reduced. SOLUTION: An encryption/decryption arithmetic circuit 100 has functions of both of an encryption arithmetic circuit which performs arithmetic operations on predetermined data, based on an AES system using an encryption key comprised of predetermined bit length, and a decryption arithmetic circuit which performs decryption arithmetic operations on the predetermined data to which the encryption arithmetic operation is performed by the encryption arithmetic circuit, based on the AES system using a decryption key comprised of the same bit length as that of the encryption key. A key schedule arithmetic circuit 200 performs processing for generating one of the encryption key and the decryption key from the other, namely, key schedule arithmetic processing. A register 300 for encryption/decryption keys performs operations for alternately storing the encryption key and the decryption key. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008294810(A) 申请公布日期 2008.12.04
申请号 JP20070139011 申请日期 2007.05.25
申请人 RENESAS TECHNOLOGY CORP 发明人 ASAMI KAZUO;YAMAGUCHI ATSUO
分类号 H04L9/10 主分类号 H04L9/10
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