| 摘要 |
A circuit structure and a method for reducing stresses on semiconductor devices fabricated underneath bondpads include metal layers with a lattice planar configuration which spreads forces applied such as during wafer test probing or during wire bonding. Easing electrical connectivity among circuit elements and maintaining circuit performance is also carried out using the lattice. The lattice has metal strips which may connect circuit elements together or which may connect to a reference voltage source. The metal layer and bondpad corners and edges are formed preferentially without acute angles.
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