| 摘要 |
<P>PROBLEM TO BE SOLVED: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. <P>SOLUTION: A silicon chip 3 is mounted on a die pad portion 4D integrated with leads 4 configuring a drain lead. The silicon chip 3 has, on the main surface thereof, a source pad 7 and a gate pad 8. The backside of the silicon chip 3 configures a drain of a power MOSFET and is bonded to the upper surface of a die pad portion 4D via an Ag paste. A lead 4 configuring a source lead is electrically coupled to the source pad 7 via an Al ribbon 10, while a lead configuring a gate lead 4 is electrically coupled to the gate pad 8 via an Au wire 11. <P>COPYRIGHT: (C)2009,JPO&INPIT |
