| 摘要 |
PROBLEM TO BE SOLVED: To provide a technology for suppressing shorting between control gate lines. SOLUTION: The semiconductor memory device comprises a semiconductor substrate 1 consisting of a memory cell array region 100 and a leading wiring region 150 adjoined to the memory cell array region 100, a memory cell MC provided to the memory cell array region 100, a contact plug CP provided to the leading wiring region 150, and a control gate line CGL which is provided from within the leading wiring region 150 down to within the memory cell array region 100, for connecting the contact plug CP to the memory cell MC. The control line CGL provided in the memory cell array region 100 contains a metal silicide 6A. The control gate line CGL provided in the leading wiring region contains no metal silicide at any one part within the leading wiring region. COPYRIGHT: (C)2009,JPO&INPIT
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