CHIP SCALE SEMICONDUCTOR PACKAGE

摘要

A chip scale semiconductor package is provided to reduce the height of semiconductor package as same as the planarization layer by reducing the planarization layer arranged between the substrate and the rerouting line of the semiconductor chip. A semiconductor package(900) comprises the substrate(100), the re-ordering wiring(300), the solder ball(400), the insulating layer(500). A semiconductor chip(200) including the integrated circuit and the connection pad(220) for exchanging the electric signal the integrated circuit is fixed. The re-ordering wiring is consecutively arranged along the top of substrate and top of the semiconductor chip. The re-ordering wiring has the wiring step height between the first area positioned on the top of the semiconductor chip and the second part positioned on the top of substrate. The re-ordering wiring is electrically connected with the connection pad. The solder ball comprises the connection part(410), and the connector area(420). The connection part is electrically connected to the re-ordering wiring. The connector area is connected to the connection part and the connector area electrically connects the external signal source and the semiconductor chip. The insulating layer is arranged on the substrate. The insulating layer electrically insulates the semiconductor chip and the re-ordering wiring.