REGISTER WITH PROCESS, SUPPLY VOLTAGE AND TEMPERATURE VARIATION INDEPENDENT PROPAGATION DELAY PATH

摘要

The digital data register has a plurality of parallel matched data paths, each data path having a data input for receiving a digital data input signal (CA/CNTRL), an output driver with a data output providing a digital data output signal (Q_CA/CNTRL) for application to an associated memory module and a flip-flop (FF1) arranged between the data input and the data output. The data register further comprises a clock input for receiving a clock input signal (CLK), a clock output for providing an output clock signal (Q_CLKn, Q_NCLKn) to the memory modules, a phase locked loop (PLL) with a clock input (REF), a feedback input (FB), a feedback output providing a feedback output signal (Q_NFB) and a clock output providing a clock output signal (Q_CLK, QNCLK). In addition a flip-flop (FF1 DELAY) and output driver replica is matched with the flip-flop and output driver of the data paths. The flip-flops (FF1) of the data paths and the flip-flop (FF1 DELAY) of the replica are clocked by the feedback signal applied to the feedback input (FB) of the phase locked loop (PLL). The phase locked loop (PLL) includes a phase aligner with a phase interpolator. The phase interpolator has an output that provides the output clock signal (Q_CLKn, Q_NCLKn) to the memory modules through a flip-flop (FF1 DELAY) and output driver matched with the flip-flop and output driver of the data paths. A phase frequency detector (PFD) has a first input (REF) coupled to the output of the output driver replica and a second input (SYS) coupled to the clock output. The phase interpolator is controlled by the output of the phase frequency detector (PFD). The proposed data register satisfies the three requirements of: (i) setup and hold timing on the pre-register side, (ii) clock centring on the post-register side, and (iii) constant propagation delay (tpd) over PVT variations from the clock input to the data output.