发明名称 BUILD-UP WIRING BOARD FOR SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a build-up wiring board that not only prevents package warpage caused at room temperature and during reflow soldering thereof even if a package baseboard is made thin but also ensures the adequate dicing characteristics when allowing a semiconductor package to be individual pieces and reflow mounting to a mounting board. SOLUTION: This invention relates to the build-up wiring board for a semiconductor device where at least either of an interlayer insulating resin layer 15 or a wiring layer 14 is laminated on surfaces A and B of a core base material 13 having wires, and a build-up wiring layer is formed by allowing each wiring layer to be electrically connected through inner via holes. In the build-up wiring board, thermal expansion coefficient in a planar direction of the interlayer insulating resin surface side A on which a semiconductor element is mounted is greater than that in the planar direction of the interlayer insulating resin of a surface side B mounted on the mounting board. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008294387(A) 申请公布日期 2008.12.04
申请号 JP20070194953 申请日期 2007.07.26
申请人 HITACHI CHEM CO LTD 发明人 KURABUCHI KAZUHIKO
分类号 H01L23/12 主分类号 H01L23/12
代理机构 代理人
主权项
地址