| 摘要 |
The invention relates to a method and a system for routing electric circuits in integrated circuit chip design. Specifically, the invention encompasses the steps of performing a congestion analysis (208) for a given routed placement of cells (11) containing said electric circuits on chip (10); defining (210) a critical area (14) on said chip (10) based on congestion information (208); analyzing (212) actual wiring quality within said critical area (14); comparing (214, 216) actual wiring quality of said critical area (14) with a reference wiring quality of said critical area (14); and rerouting (218) said critical area (14) based on a comparison (216) between actual wiring quality and reference wiring quality.
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