| 摘要 |
There is disclosed a semiconductor memory device in which, activation timing control of a plurality of word lines of a plurality of ports is managed based on a plurality of clock signals, test signals are provided in association with the plurality of clock signals respectively controlling the activation timings of the word lines of the plurality of ports. If, with the cell, with the plurality of ports selected, the one test signal is in an activated state and the other test signal is in a non-activated state, activation of word lines of the plurality of ports is controlled in response to one clock signal, with the other clock signal being then masked. The timing difference, inclusive of the zero timing difference, between the activation timing of the plurality of word lines of the plurality of port may be finely adjusted by a delay control signal.
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