发明名称
摘要 <p>Disclosed is a block select circuit in a flash memory device. The block select circuit comprises a select unit including a flash memory cell that is programmable and erasable by a given voltage condition, for outputting a block select signal depending on address signals and a state of the flash memory cell, a high-voltage pumping unit for outputting a signal to keep a given high voltage according to the block select signal and the clock signal, and a switching unit for applying a given bias to a gate select line, a word line and a source select line of a flash memory cell block according to the output signal of the high-voltage pumping unit. A given voltage is not applied to a fail block by only the operation of programming the flash memory cell of an erase state. Therefore, it is possible to process a fail block even after being packaged.</p>
申请公布号 JP4190970(B2) 申请公布日期 2008.12.03
申请号 JP20030272938 申请日期 2003.07.10
申请人 发明人
分类号 G11C16/06;G11C29/04;G11C8/12;G11C11/34;G11C16/02;G11C16/08;G11C16/12;G11C29/00 主分类号 G11C16/06
代理机构 代理人
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