发明名称 |
Layout method of a semiconductor memory device |
摘要 |
The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.
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申请公布号 |
US7460386(B2) |
申请公布日期 |
2008.12.02 |
申请号 |
US20070790444 |
申请日期 |
2007.04.25 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHO BEAK-HYUNG;KIM DU-EUNG;CHOI BYUNG-GIL;KWAK CHOONG-KEUN |
分类号 |
G11C5/02;G11C5/06;G11C11/00 |
主分类号 |
G11C5/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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