发明名称 Modular multiplier
摘要 Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.
申请公布号 US7461115(B2) 申请公布日期 2008.12.02
申请号 US20030387009 申请日期 2003.03.11
申请人 SUN MICROSYSTEMS, INC. 发明人 EBERLE HANS;GURA NILS;BROWN RUSSELL A.;CHANG-SHANTZ SHEUELING;GUPTA VIPUL
分类号 G06F7/00;G06F7/527;G06F7/72;G06F15/00;H04L9/00 主分类号 G06F7/00
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